Stanford accelerate group works on creating high performance and energy-efficient architectures and design methodology for domain-specific hardware accelerators in existing and emerging technologies.
Email: praina AT stanford DOT edu
Contact: Allen Building - Room 114
About: Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University. She received her BTech in Electrical Engineering from the IIT Delhi in 2011 and her SM and PhD in Electrical Engineering and Computer Science from MIT in 2013 and 2018. Priyanka’s research is on creating high-performance and energy-efficient architectures for domain-specific hardware accelerators in existing and emerging technologies and agile hardware-software co-design. Her research has won best paper awards at VLSI, ESSCIRC and MICRO conferences and in the JSSC journal. Priyanka teaches several VLSI design classes at Stanford. She has also won the Intel Rising Star Faculty Award, Hellman Faculty Scholar Award and is a Terman Faculty Fellow.
Email: akashl AT stanford DOT edu, Webpage
About: Akash Levy is an EE Ph.D. student at Stanford University, supervised by Prof. Priyanka Raina. Previously, he was a Research Intern at Amazon Lab126 and Amazon Web Services. He received a B.S.E. degree in Electrical Engineering from Princeton University in 2018, with certificates in Applications of Computing and Engineering Physics. He is a recipient of the NSF Graduate Research Fellowship.
Research: His current research is focused on improving the efficiency of reconfigurable logic devices (such as FPGAs and CGRAs) through the use of 3D integration with emerging nanotechnologies. In particular, he is developing a hybrid design that makes use of both resistive random access memory (RRAM) and nanoelectromechanical (NEM) relays to implement reconfigurable switching in the back-end-of-line for reduced reconfigurability overhead. His goal is to enable reconfigurable logic devices to become more competitive with ASICs in terms of power, area, and performance. His pre-PhD research involved a broad range of subjects, ranging from physics to computer security. For more details, please refer to his Academia.edu portfolio and Google Scholar profile.
Email: kzf AT stanford DOT edu, Webpage
About: Kathleen Feng is an EE Ph.D. student at Stanford University, supervised by Prof. Priyanka Raina. She received a B.S.E. degree in Electrical Engineering from Princeton University in 2018, with certificates in Applications of Computing and Robotics and Intelligent Systems. She is a recipient of the NDSEG Fellowship.
Research: Her research focuses on domain-specific hardware architectures and hardware-software co-design. She has worked on coarse-grained reconfigurable arrays for application acceleration and systems for running extended reality applications. Kathleen is interested in designing and developing new computer architectures for emerging applications.
Email: melchert AT stanford DOT edu
About: Jackson Melchert is an EE Ph.D. student at Stanford University, supervised by Prof. Priyanka Raina. He received a B.S. in Electrical and Computer Engineering and Computer Science from the University of Wisconsin - Madison in 2019.
Research: His research focuses on how to generate an optimal coarse-grained reconfigurable array processing element (PE) architecture for a given application domain. He is developing tools to analyze the applications that are going to be run on the CGRA to identify interesting PE architectures to be evaluated. He is also developing a PE generator that takes a high level specification of a PE from the application analysis and produces the hardware description of the PE, along with functional and formal models used in the application mapping process. Jack is broadly interested in optimizing configurable hardware to approach the performance and efficiency of application-specific accelerators.
Email: kkoul AT stanford DOT edu, Webpage
About: Kalhan Koul is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. Previously, he was a Digital Design Intern at Micron and Silicon Labs. He received a B.S. in Electrical Engineering Honors and a B.A. in Plan II Honors (Liberal Arts) from The University of Texas in 2018.
Research: My current research focuses on automatically mapping applications, ranging from machine learning to image processing, onto reconfigurable logic devices (CGRAs). Previously, I helped design and tape-out a DNN accelerator utilizing resistive memory (RRAM) for low-energy inference and training. This chip exploited the low read cost and non-volatility of RRAM to store the weights of a DNN model, providing a low energy solution for edge and IoT devices. Broadly speaking, I am interested in improving the hardware design flow and developing highly performant and flexible hardware.
Email: kprabhu7 AT stanford DOT edu, Webpage
About: Kartik Prabhu is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received an M.S. degree in Electrical Engineering from Stanford University in 2021 and a B.S. degree in Computer Engineering from Georgia Institute of Technology in 2018.
Research: His research focuses on building energy-efficient machine learning accelerators. In particular, he is looking at leveraging emerging memory technologies, such as resistive RAM (RRAM), to solve the challenges of machine learning inference and training at the edge.
Email: pohan AT stanford DOT edu, Webpage
About: Po-Han Chen is an EE Ph.D. student at Stanford University supervised by Prof. Priyanka Raina. He received his B.S. in Electrical Engineering and Computer Science (EECS) and M.S. in Electrical Engineering from National Tsing Hua University (Taiwan) in 2016 and 2018 respectively. Before joining Stanford, he was a digital circuit designer at MediaTek where he worked on developing hardware architectures of image processing pipeline.
Research: I am generally interested in designing hardware accelerators. Most of my previous works were related to computational photography algorithms such as digital refocusing. Currently, I am focusing on analyzing and designing architecture of CGRAs to create high-performance, energy-efficient, and reconfigurable computing platforms.
Email: jeffreyy AT stanford DOT edu
About: Jeffrey is an EE Master student at Stanford University working in Prof. Priyanka Raina’s research group. He received his B.S. degree in Computer Engineering from UC San Diego in 2021.
Research: My research focuses on efficient DNN inference and training using quantization and new number systems. I also work on the mapping DNN operations to the accelerator and verification of RTL and SoC.
Email: yuchenm AT stanford DOT edu, Webpage
About: Yuchen Mei is an EE M.S. student at Stanford University supervised by Prof. Priyanka Raina. He received a B.S. degree in Electronic Information Science and Technology from Nanjing University (China) in 2021. Before joining Stanford, he was a research assistant at Nanjing University where he worked on 3D-CNN optimization and hardware security.
Research: Currently, my research focuses on how to improve the frequency of image processing and machine learning applications running on CGRAs. I am involved in the development of software pipelining techniques and the design space exploration of the CGRA array and interconnection system. I am generally interested in chip design, domain-specific accelerators, and design automation.
Email: bmccolm AT stanford DOT edu
About: Brianna McColm is an M.S. EE student at Stanford University. She received her B.S. in Electrical Engineering from UCLA in 2022. Previously, she was a Firmware Engineering Intern for Qualcomm and an RF/uW Engineering Intern for Keysight Technologies.
Research: Brianna is interested in hardware accelerators and how bridging the hardware-software gap can boost system performance.
Email: xingyuni AT stanford DOT edu
About: Xingyu Ni is an EE M.S. student at Stanford University. She received a B.S. degree in Electrical Engineering from Tianjin University in 2021.
Research: My current research focuses on FPGA implementation of AR/VR applications.
Email: peggylin AT stanford DOT edu
About: Peggy is an EE M.S. student at Stanford University. She received her B.S. in Electrical Engineering from the National Taiwan University (Taiwan) in 2022.
Research: Her research focuses on the memory tile of CGRAs. She is interested in design exploration of CGRAs to create high-performance, energy-efficient, and flexible hardware.
Email: jespera AT stanford DOT edu
About: John Espera is an EE M.S. student at Stanford University. He received a B.Eng. in Electronic Engineering from the University of Warwick in 2021.
Research: His research involves developing new applications to map onto reconfigurable logic devices (CGRAs) using the Halide language.
Email: cterrill AT stanford DOT edu
About: Caleb is an EE M.S. student at Stanford. He received his B.S. in Computer Engineering from UCLA in 2022. Previously, he has interned as an FPGA designer at Jane Street and as an IP designer at Apple and Intel.
Research: His research relates to the generation and verification of the compiler for CGRA programs. In the fall of 2022, he utilized SMT-based tools to verify the functionality of pipelined compute mappings to CGRA processing elements (PEs). This year, he focuses on improving rewrite rule synthesis to enable many-to-many rewrite rules.
Email: klinej AT stanford DOT edu
Contact: Packard Building - Room 359
About: Julie Kline is a Faculty Administrator at Stanford, and she supports several Electrical Engineering professors and their research teams. She holds a master’s degree in English from San Jose State University, and prior to her work at Stanford, she spent several years teaching academic writing and rhetoric at De Anza College in Cupertino. Julie is an active member at Coastal Repertory Theatre in Half Moon Bay, where in addition to acting, directing, and producing, she serves on several committees and the Board of Directors.