Publications

  • S. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, B. Dally, J. Emer, C. T. Gray, B. Khailany, S. Keckler, “Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture”, to be presented at IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct 2019.
  • R. Venkatesan, S. Shao, M. Wang, J. Clemons, S. Dai, M. Fojtik, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, Y. Zhang, B. Zimmer, B. Dally, J. Emer, S. Keckler, B. Khailany, “MAGNet: A Modular Accelerator Generator for Neural Networks”, to be presented at IEEE/ACM International Conference On Computer Aided Design (ICCAD), Nov 2019.
  • R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, N. Chizgi, R. G. Daly, C. Donovick, D. Durst, K. Fatahalian, P. Hanrahan, T. Hofstee, M. Horowitz, D. Huff, T. Kong, Q. Liu, M. Mann, A. Nayak, A. Niemetz, G. Nyengele, P. Raina, S. Richardson, R. Setaluri, J. Setter, D. Stanley, M. Strange, J. Thomas, L. Truong, X. Yang, K. Zhang, “Creating An Agile Hardware Flow”, to be presented at HotChips 2019.
  • B. Khailany, R. Venkatesan, Y. S. Shao, B. Zimmer, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. G. Tell, Y. Zhang, W. J. Dally, J. S. Emer, C. T. Gray, S. W. Keckler, “A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology”, to be presented at HotChips 2019.
  • B. Zimmer, R. Venkatesan, Y. S. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. G. Tell, Y. Zhang, W. J. Dally, J. S. Emer, C. T. Gray, S. W. Keckler, B. Khailany, “A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm”, to be presented at VLSI 2019.
  • A. Parashar, P. Raina, S. Shao, A. Mukkara, V. A. Ying, R. Venkatesan, Y. H. Chen, B. Khailany, S. Keckler, J. Emer, “Tensorloop: A Systematic Approach to DNN Accelerator Evaluation”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2019. Paper
  • P. Raina, M. Tikekar, and A. P. Chandrakasan, “An energy-scalable accelerator for blind image deblurring,” in IEEE Journal of Solid-State Circuits (JSSC) - ESSCIRC Special Issue, July 2017. (Invited) Paper
  • P. Raina, M. Tikekar, and A. P. Chandrakasan, “An energy-scalable accelerator for blind image deblurring,” in IEEE European Solid-State Circuits Conference (ESSCIRC), Sep 2016, pp. 113-116. Paper
  • D. Jeon, N. Ickes, P. Raina, H. C. Wang, A. P. Chandrakasan, “24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016. Paper
  • R. Rithe, P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, “Reconfigurable Processor for Energy-Efficient Computational Photography,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 11, pp. 2908-2919, Nov. 2013. Paper
  • R. Rithe, P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, “Reconfigurable Processor for Energy-Scalable Computational Photography,” IEEE International Solid-State Circuits Conference (ISSCC), 164-165, February 2013. Paper